1. Field of the Invention
This invention relates to field-effect transistor (FET) circuits for providing a low-power, implementation of biphase signal processing suitable for such uses as microwave phase logic (MPL) and signal transmission for input to, output from and within large monolithic integrated-circuit (IC) chips and, more particularly, to passive and/or semi-passive FET circuits preferably employing pseudomorphic high-electron-mobility transistors (PHEMT) for microwave or very high frequency operation thereof.
2. Description of the Prior Art
Two different known ways of implementing digital encoding of information in binary form comprise pulse encoding and biphase encoding. In pulse encoding, which is often implemented by monolithic IC's performing digital processing, two switchable binary states are distinguished from on another by a sufficiently large minimum difference in voltage amplitude levels to prevent any ambiguity between them. In biphase encoding, which is often used for the wireless transmission of binary informational microwave frequencies, one of two binary states is represented by a predetermined frequency, fixed-amplitude signal having one certain phase (e.g., +.pi./2) and the other of two binary states is represented by the predetermined frequency fixed-amplitude signal having a phase (e.g., -.pi./2) opposite to the one certain phase.
Incorporated herein by reference are the teachings of U.S. Pat. Nos. 5,528,174 and its division 5,528,175, assigned to the assignee of the present application, which disclose various logic devices that employ biphase encoding for implementing microwave phase logic (MPL) operating at multigigabits per second rates. A first approach taught in these two patents, which may be implemented by a monolithic IC, employs multigate active FET circuits. However, a second approach taught in these two patents, which cannot be implemented by a monolithic IC, employs doubly-balanced mixers that can be operated, in some cases, as a modulator or, in other cases, as a demodulator. More specifically, as known, a doubly-balanced mixer employs a quad of 4 diodes connected in a ring together with an input balun and an output balun. Such baluns, operating at very high RF or microwave frequencies require transformers or other types of mutual coupling devices that are not amenable to implementation by a monolithic IC. Further, incorporated herein by reference is the teaching of U.S. Pat. No. 6,008,748, assigned to the assignee of the present application, which is directed to various MPL implementations of analog-to-digital (A/D) converters all of which employ such above-described doubly-balanced mixers that can be operated, in some cases, as a modulator or, in other cases, as a demodulator.
Recent advances in monolithic IC technology have made it possible to fabricate larger and larger chip-size ICs. Also, recent advances in microlithographic techniques make it practical to fabricate FETs with much smaller dimensions, thereby thereby permitting a large-size chip-IC to comprise a vast number (e.g., millions) of smaller-area individual FETs that are able to operate efficiently at substantially higher clock frequencies (where such clock frequencies may have a value of many hundreds of megahertz (MHz) or even of a multigigahertz microwave frequency). At such high clock frequencies, it is desirable to employ low characteristic impedance (e.g., 50 ohm) transmission lines to transmit digital signals from (1) an input device to an IC chip, (2) an output from one IC chip as an input to another IC chip and/or (3) an output from an IC chip to an output device. Further, because of the very large IC chip size, there may be a need to employ such a low characteristic impedance transmission line to transmit a digital signal derived at a first physical location on the IC chip to a second physical location on the IC chip which is relatively distant from the first physical location on the IC chip. In addition, very large IC chips tend to have a large number of individual inputs and output (I/O) ports. Each of these I/O ports must be properly impedance matched to the low-impedance transmission line with which it is associated and the power applied to each transmission line that is transmitted thereover must be at least sufficient to provide a signal-to-noise ratio high enough to provide substantially error-free data transmission.
Currently, each transmission line input tends to be powered by an individual driver responsive to pulse-encoded applied data, which driver has an output substantially matching the low (e.g., 50 ohm) characteristic impedance of the transmission line, while each transmission line output is terminated by a circuit having an input impedance substantially matching the low (e.g., 50 ohm) characteristic impedance of the transmission line. As pointed out above, pulse-encoded data requires a relatively large difference in voltage amplitude levels to prevent any ambiguity between binary states. Further switching between such binary states results in transients that increase noise, thereby increasing the power needed to be generated by each individual driver. Thus, if the low-impedance transmission line drivers are responsive to pulse-encoded data, the total power needed to be generated by all these drivers on a very-large monolithic chip cause undesirable high heating and high noise problems.
In biphase-encoded data, discussed above, wherein the phase of a fixed amplitude predetermined frequency signal may be either +.pi./2 or -.pi./2 in accordance with the current binary state of the data, inherently results in the generation of significantly lower switching noise (a higher signal-to-noise ratio) than is generated by pulse-encoded data. This is one reason that it is desirable in the case of a very large-size monolithic IC chip to employ drivers which generate biphase-encoding for transmitting very-high or microwave frequency data over the large number of low-impedance transmission lines associated with such a very large-size monolithic IC chip, even when the data to be digitally processed by this very large-size monolithic IC chip is to be implemented in pulse-encoded form.
One object of the present invention is to employ novel FET circuits to achieve significantly lower power biphase-encoded drivers and termination circuits for the large number of low-impedance transmission lines associated with such a very large-size monolithic IC chip than could be achieved using prior-art drivers and termination circuits.
Another object of the present invention is to employ novel FET circuits to achieve biphase-encoded MPL implemented on a monolithic IC chip.
While the FETs employed in the novel FET circuits of the present invention, described in detail below, may be FETs fabricated either of silicon or gallium arsenide, gallium-arsenide PHEMT FETs are preferable when operation is desired at a multigigahertz frequency, since, as known in the art, PHEMT FETs are particularly suitable for operation at multigigahertz frequencies.